CV

My academic curriculum vitae.

Contact Information

Name Eliott Quéré
Professional Title PhD Student in Hardware Security
Email

Professional Summary

PhD student at Université de Rennes / IRISA / Inria / CNRS, SUSHI Team (CentraleSupélec). Research interests span hardware security, computer architecture, and reconfigurable computing. Currently visiting ISEC, TU Graz. Former Detection Engineer at Ministère des Armées and intern at Apple Inc.

Experience

  • 2026 -

    Graz, Austria

    Visiting PhD Student
    ISEC, TU Graz
    On-site collaboration with Daniel Gruss’s group. Working on side-channel attacks on SoC devices.
  • 2024 -

    Rennes, France

    Doctoral Researcher
    Université de Rennes / IRISA / INRIA — SUSHI Team (CentraleSupélec)
    Research on the security of heterogeneous SoC-FPGA platforms for cloud and edge computing.
    • Focusing on leakage risks from shared hardware resources and multi-tenant execution.
    • Study of microarchitectural behavior through embedded power sensing rather than traditional timing analysis.
    • Development of MIRABELLE, a framework combining on-chip sensing and signal processing to identify leakage sources invisible to software-only observation.
  • 2021 - 2024

    Rennes, France

    Detection Engineer
    Ministère des Armées
    • Designed graph-based models (Tid2Vec) to represent MITRE ATT&CK techniques and infer semantic relationships.
    • Built an unsupervised Transformer-based pipeline for event-log analysis, including noise reduction and automatic pattern extraction.
  • 2023 - 2023

    London, United Kingdom

    Detection Engineering Intern
    Apple Inc.
    • Optimized large-scale security telemetry with Databricks and Apache Spark, reducing false positives in detection workflows.
  • 2021 - 2021

    Rennes, France

    Security Engineering Intern
    Ministère des Armées
    • Designed and deployed a multi-antivirus sandbox platform for malware detection and behavioral analysis.

Education

  • 2024 -

    Rennes, France

    Ph.D.
    Université de Rennes / IRISA / INRIA / SUSHI Team (CentraleSupélec)
    Hardware Security
    • Supervisors: Lilian Bossuet, Rubén Salvador, Maria Méndez Real, Alessandro Palumbo, Thomas Rokicki.
    • PROACT Training School (Crete, June 2025): hardware security, side-channel analysis, embedded cryptography.
    • MICSEC International Winter School on Microarchitectural Security (Télécom Paris, December 2025).
  • 2021 - 2024

    Brest, France

    Diplôme d'Ingénieur
    IMT Atlantique
    Telecommunications, Networks, and Computer Engineering
    • Research program: advanced musical source separation (segmentation models, Transformer ViT autoencoders).
    • Project: modular FPGA synthesizer for frequency-domain processing and real-time sound synthesis.
  • 2019 - 2021

    Saint-Malo, France

    Bachelor's Degree
    Université de Rennes — IUT de Saint-Malo
    Networks and Telecommunications

Skills

Programming: C / C++, Python, Scala, Go, ARM Assembly
Hardware / FPGA: Vivado, Vitis, Verilog, VHDL
Technologies: Linux, Git, Docker, TensorFlow, PyTorch, Spark
Languages: French (native), English (fluent), German (B1)