Eliott Quéré

IRISA — SUSHI Team

Rennes, France

I am a PhD student at IRISA (Université de Rennes, Inria, CNRS) in the SUSHI Team at CentraleSupélec, working on the security of heterogeneous SoC-FPGA platforms for cloud and edge computing.

My research lies at the intersection of hardware security and microarchitecture, focusing on leakage risks from shared hardware resources: I study microarchitectural behavior through embedded power sensing rather than traditional timing analysis.

I have deep experience in data science applied to information security, with a strong focus on threat hunting and detection engineering, enriched by my work at Apple and the Ministère des Armées. I am also deeply interested in low-level hardware from a security perspective.

news

Mar 21, 2026	Paper accepted at IEEE HOST 2026 (Washington DC): SnoopyPower! Remote Power Attacks on Cache and Coherence Paths. Joint work with M. Méndez Real, A. Palumbo, T. Rokicki, L. Bossuet, and R. Salvador.
Mar 01, 2026	Currently a visiting PhD student at ISEC, TU Graz, collaborating with Daniel Gruss’s group on side-channel attacks on SoC devices.
Dec 01, 2025	Attended MICSEC 2025 International Winter School on Microarchitectural Security at Télécom Paris — cryptography, side channels, transient execution attacks, and formal methods for security.
Jun 04, 2025	Attended PROACT Training School 2025 in Crete — hardware security, side-channel analysis, and embedded cryptography.
Jun 01, 2025	Paper accepted at RESSI 2025: Side-Channel Exploitation of DRAM Access Patterns for Fingerprinting FPGA-CPU Environments. Joint work with M. Méndez Real, A. Palumbo, L. Bossuet, and R. Salvador.

latest posts

selected publications

HOST
SnoopyPower! Remote Power Attacks on Cache and Coherence Paths

Eliott Quéré, Maria Méndez Real, Alessandro Palumbo, and 3 more authors

In IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2026

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We demonstrate that cache coherence protocol decisions can be remotely observed through on-chip power measurements on heterogeneous SoC-FPGA platforms, enabling a new class of side-channel attacks that bypass traditional software-level countermeasures.
@inproceedings{quere2026snoopypower, title = {SnoopyPower! Remote Power Attacks on Cache and Coherence Paths}, author = {Qu{\'e}r{\'e}, Eliott and M{\'e}ndez Real, Maria and Palumbo, Alessandro and Rokicki, Thomas and Bossuet, Lilian and Salvador, Rub{\'e}n}, booktitle = {IEEE International Symposium on Hardware Oriented Security and Trust (HOST)}, year = {2026}, address = {Washington DC, USA}, month = may, }
RESSI
Side-Channel Exploitation of DRAM Access Patterns for Fingerprinting FPGA-CPU Environments

Eliott Quéré, Maria Méndez Real, Alessandro Palumbo, and 2 more authors

In Rendez-Vous de la Recherche et de l’Enseignement de la Sécurité des Systèmes d’Information (RESSI), May 2025

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In multi-tenant FPGA-accelerated cloud platforms, independent users share the same reconfigurable fabric and underlying hardware resources. This work investigates how DRAM access patterns observable through side-channel measurements can be exploited to fingerprint FPGA-CPU environments, enabling co-location detection and infrastructure reconnaissance in reconfigurable cloud scenarios.
@inproceedings{quere2025side, title = {Side-Channel Exploitation of DRAM Access Patterns for Fingerprinting FPGA-CPU Environments}, author = {Qu{\'e}r{\'e}, Eliott and M{\'e}ndez Real, Maria and Palumbo, Alessandro and Bossuet, Lilian and Salvador, Rub{\'e}n}, booktitle = {Rendez-Vous de la Recherche et de l'Enseignement de la S{\'e}curit{\'e} des Syst{\`e}mes d'Information (RESSI)}, year = {2025}, address = {Lanniron, France}, month = may, }