We demonstrate that cache coherence protocol decisions can be remotely observed through on-chip power measurements on heterogeneous SoC-FPGA platforms, enabling a new class of side-channel attacks that bypass traditional software-level countermeasures.
@inproceedings{quere2026snoopypower,title={SnoopyPower! Remote Power Attacks on Cache and Coherence Paths},author={Qu{\'e}r{\'e}, Eliott and M{\'e}ndez Real, Maria and Palumbo, Alessandro and Rokicki, Thomas and Bossuet, Lilian and Salvador, Rub{\'e}n},booktitle={IEEE International Symposium on Hardware Oriented Security and Trust (HOST)},year={2026},address={Washington DC, USA},month=may,}
2025
RESSI
Side-Channel Exploitation of DRAM Access Patterns for Fingerprinting FPGA-CPU Environments
Eliott Quéré, Maria Méndez Real, Alessandro Palumbo, and 2 more authors
In Rendez-Vous de la Recherche et de l’Enseignement de la Sécurité des Systèmes d’Information (RESSI), May 2025
In multi-tenant FPGA-accelerated cloud platforms, independent users share the same reconfigurable fabric and underlying hardware resources. This work investigates how DRAM access patterns observable through side-channel measurements can be exploited to fingerprint FPGA-CPU environments, enabling co-location detection and infrastructure reconnaissance in reconfigurable cloud scenarios.
@inproceedings{quere2025side,title={Side-Channel Exploitation of DRAM Access Patterns for Fingerprinting FPGA-CPU Environments},author={Qu{\'e}r{\'e}, Eliott and M{\'e}ndez Real, Maria and Palumbo, Alessandro and Bossuet, Lilian and Salvador, Rub{\'e}n},booktitle={Rendez-Vous de la Recherche et de l'Enseignement de la S{\'e}curit{\'e} des Syst{\`e}mes d'Information (RESSI)},year={2025},address={Lanniron, France},month=may,}